The manufacture of integrated circuits generally, and dynamic random access memories (DRAMs) particularly, involves hundreds of individual manufacturer or process steps. While any generalization of such a large number of operations necessarily omits much detail, the manufacture of integrated circuits can be generally described with four major divisions: prepare blank wafers of semiconductor material, such as silicon; process the blank wafers to form multiple chips containing the desired circuits; package the individual chips and subject the packaged chips to elevated temperature and voltage operating conditions to eliminate early failing chips, e.g. perform burn-in testing. This last step helps ensure reliability.
To reduce the cost of memory devices, efforts are continuously being made to reduce the number of manufacturing or process steps required to fabricate devices. One objective of cost reduction has been addressed by the DRAM industry in the form of mask reduction; that is, attempting to fabricate the desired DRAM design, while using fewer costly photolithographic steps.
Complementary metal-oxide-semiconductor (CMOS) is the most common technology used to form DRAM devices. As is known, CMOS circuits include both n-channel and p-channel transistors. The choice of the gate material and the channel doping level determines the threshold voltage for the transistors. For enhanced performance of the devices, it is desirable that the threshold voltages of the n- and p-channel transistors are comparable, and preferably, of equal magnitude. It is also desirable that the threshold voltages are as low as possible without introducing excessive off-state current.
The most common choice for gate material for modern CMOS technologies is n-type polysilicon that is doped heavily enough to make the polysilicon degenerate. This is usually combined with a silicide layer to lower the sheet resistance. The work function of n+ polysilicon is ideal for an n-channel device since it yields a threshold voltage of less than 0.7 V for reasonable values of channel doping and oxide thickness.
When the n+ polysilicon gate is used, the p-channel threshold voltage is not as ideally adjusted with the substrate doping. The threshold voltage of the p-channel device is adjusted by simply reducing the p-channel substrate doping. For doping levels necessary to prevent short-channel effects, the threshold voltage magnitude is above 1 V.
A technique that allows the p-channel threshold voltage to be adjusted to the desired level is to implant a shallow boron layer into the channel region. The boron shifts the threshold voltages towards more positive values by forming a compensating layer. The boron threshold adjustment can also be used to raise the threshold voltage of the n-channel transistor. A single boron implant dose can be used to set the threshold voltages of both the n- and p-channel transistors if the background dopings are chosen correctly. The magnitude of VTP, the threshold voltage of the p-channel transistor, is reduced because the boron implant charge to the channel region of the n-well. Lower n-well doses allow the boron implant to have a greater effect on the value of VTP. One disadvantage to this approach is that the p-channel transistor is more susceptible to short-channel effects with the compensated surface channel.
Another choice for the gate material is p+-polysilicon. The work function of p+ polysilicon is about 1.1 V greater than for n+ polysilicon. This makes it ideal for the p-channel transistor in terms of having the threshold voltage easily adjusted to −0.7 V or less with channel doping of 1015 to 1017 cm−3. However, the n-channel transistor must now be compensated to reduce the threshold voltage to reasonably low values.
Other choices of gate material, such as MoSi2, have metal work functions that are between those of n+ and p+ polysilicon, which allows both transistors to be slightly compensated to get the desired threshold voltages. To optimize both devices simultaneously, both n+- and p+-type polysilicon gates can be used for the n- and p-channel transistors respectively. This approach allows both transistor threshold voltages to be easily adjusted to the desired threshold voltages without sacrificing short-channel effects, but adds to the processing complexity. See S. M. Sze, VLSI Technology, McGraw-Hill, New York, 1988, Ch. 11, pp. 483-493.